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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This file contains a interrupt mode design example for the Device Configuration Interface. </p>
<p>This example downloads a given bitstream to the FPGA fabric.</p>
<p>BIT_STREAM_LOCATION specifies the memory location of the bitstream. BIT_STREAM_SIZE_WORDS specifies the size of the bitstream in words. User has to define these correctly for this example to work.</p>
<dl class="section note"><dt>Note</dt><dd>None</dd></dl>
<p>MODIFICATION HISTORY:</p>
<pre>
  Ver   Who  Date     Changes
</p>
<hr/>
<p>
  1.00a hvm  02/07/11 First release
  1.00a nm   11/26/11 Holding FPGA in reset before download and
                      releasing it after bitstream download. This code
                      is not checking bitstream download errors.
                      If the bitstream download fails, this test hangs.
  2.00a nm   05/31/12 Updated the notes in the example for CR 660139 to add
                      information that the 2 LSBs of the Source/Destination
                      address when equal to 2�b01 indicate the last DMA command
                      of an overall transfer.
                      Updated the example for CR 660835 so that input length for
                      source/destination to the XDcfg_Transfer APIs is words
                      (32 bit) and not bytes.
  2.01a nm   11/21/12 Fixed CR# 688146. Modified the bitstream address.
  2.02a nm   01/31/13 Fixed CR# 679335.
                      Removed disabling and enabling AXI interface.
                      Clearing the interrupts before the transfer.
                      Added support for partial reconfiguration.
  3.00a kpc  02/10/14 Fixed the compilation error
  3.1   kpc  04/22/14 Fixed CR#780203. Enable the pcap clock if it is not set.
        ms   04/10/17 Modified filename tag to include the file in doxygen
        ms   04/10/17 Modified filename tag to include the file in doxygen
                      examples.
  3.8  Nava  06/21/23 Added support for system device-tree flow.
*</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a286f17de7ab3285f143c9aab3fc26da4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#a286f17de7ab3285f143c9aab3fc26da4">SLCR_LOCK</a>&#160;&#160;&#160;0xF8000004</td></tr>
<tr class="memdesc:a286f17de7ab3285f143c9aab3fc26da4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection Lock.  <a href="#a286f17de7ab3285f143c9aab3fc26da4">More...</a><br/></td></tr>
<tr class="separator:a286f17de7ab3285f143c9aab3fc26da4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83fcf6f141c914ab6b8b683fb62232b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#a83fcf6f141c914ab6b8b683fb62232b4">SLCR_UNLOCK</a>&#160;&#160;&#160;0xF8000008</td></tr>
<tr class="memdesc:a83fcf6f141c914ab6b8b683fb62232b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Write Protection Unlock.  <a href="#a83fcf6f141c914ab6b8b683fb62232b4">More...</a><br/></td></tr>
<tr class="separator:a83fcf6f141c914ab6b8b683fb62232b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af11ce8b1924394e9c6d481b9f4fd45dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#af11ce8b1924394e9c6d481b9f4fd45dd">SLCR_LVL_SHFTR_EN</a>&#160;&#160;&#160;0xF8000900</td></tr>
<tr class="memdesc:af11ce8b1924394e9c6d481b9f4fd45dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR Level Shifters Enable.  <a href="#af11ce8b1924394e9c6d481b9f4fd45dd">More...</a><br/></td></tr>
<tr class="separator:af11ce8b1924394e9c6d481b9f4fd45dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4bb19a9df26550ba4c6fcaaddf516f18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#a4bb19a9df26550ba4c6fcaaddf516f18">SLCR_PCAP_CLK_CTRL</a>&#160;&#160;&#160;XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168</td></tr>
<tr class="memdesc:a4bb19a9df26550ba4c6fcaaddf516f18"><td class="mdescLeft">&#160;</td><td class="mdescRight">SLCR PCAP clock control register address.  <a href="#a4bb19a9df26550ba4c6fcaaddf516f18">More...</a><br/></td></tr>
<tr class="separator:a4bb19a9df26550ba4c6fcaaddf516f18"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a2a07952c85939f2590c00f736e075bd1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample</a> (XScuGic *IntcInstPtr, <a class="el" href="struct_x_dcfg.html">XDcfg</a> *DcfgInstPtr, u16 DeviceId, u16 DcfgIntrId)</td></tr>
<tr class="memdesc:a2a07952c85939f2590c00f736e075bd1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function downloads the Non secure bit stream to the FPGA fabric using the Device Configuration Interface.  <a href="#a2a07952c85939f2590c00f736e075bd1">More...</a><br/></td></tr>
<tr class="separator:a2a07952c85939f2590c00f736e075bd1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a840291bc02cba5474a4cb46a9b9566fe"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdevcfg__interrupt__example_8c.html#a840291bc02cba5474a4cb46a9b9566fe">main</a> (void)</td></tr>
<tr class="memdesc:a840291bc02cba5474a4cb46a9b9566fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Main function to call the polled mode example.  <a href="#a840291bc02cba5474a4cb46a9b9566fe">More...</a><br/></td></tr>
<tr class="separator:a840291bc02cba5474a4cb46a9b9566fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a286f17de7ab3285f143c9aab3fc26da4"></a>
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<div class="memproto">
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          <td class="memname">#define SLCR_LOCK&#160;&#160;&#160;0xF8000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SLCR Write Protection Lock. </p>

<p>Referenced by <a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample()</a>.</p>

</div>
</div>
<a class="anchor" id="af11ce8b1924394e9c6d481b9f4fd45dd"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define SLCR_LVL_SHFTR_EN&#160;&#160;&#160;0xF8000900</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SLCR Level Shifters Enable. </p>

<p>Referenced by <a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample()</a>.</p>

</div>
</div>
<a class="anchor" id="a4bb19a9df26550ba4c6fcaaddf516f18"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SLCR_PCAP_CLK_CTRL&#160;&#160;&#160;XPAR_PS7_SLCR_0_S_AXI_BASEADDR + 0x168</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SLCR PCAP clock control register address. </p>

<p>Referenced by <a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample()</a>.</p>

</div>
</div>
<a class="anchor" id="a83fcf6f141c914ab6b8b683fb62232b4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define SLCR_UNLOCK&#160;&#160;&#160;0xF8000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SLCR Write Protection Unlock. </p>

<p>Referenced by <a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample()</a>.</p>

</div>
</div>
<h2 class="groupheader">Function Documentation</h2>
<a class="anchor" id="a840291bc02cba5474a4cb46a9b9566fe"></a>
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          <td class="memname">int main </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Main function to call the polled mode example. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS if successful, XST_FAILURE if unsuccessful.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xdevcfg__interrupt__example_8c.html#a2a07952c85939f2590c00f736e075bd1">XDcfgInterruptExample()</a>.</p>

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<a class="anchor" id="a2a07952c85939f2590c00f736e075bd1"></a>
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          <td class="memname">int XDcfgInterruptExample </td>
          <td>(</td>
          <td class="paramtype">XScuGic *&#160;</td>
          <td class="paramname"><em>IntcInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_dcfg.html">XDcfg</a> *&#160;</td>
          <td class="paramname"><em>DcfgInstPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DcfgIntrId</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function downloads the Non secure bit stream to the FPGA fabric using the Device Configuration Interface. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">IntcInstPtr</td><td>is a pointer to the instance of the Scu GIC driver. </td></tr>
    <tr><td class="paramname">DcfgInstPtr</td><td>is a pointer to the instance of <a class="el" href="struct_x_dcfg.html" title="The XDcfg driver instance data. ">XDcfg</a> driver. </td></tr>
    <tr><td class="paramname">DeviceId</td><td>is the unique device id of the device. </td></tr>
    <tr><td class="paramname">DcfgIntrId</td><td>is the interrupt Id.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS if successful, otherwise XST_FAILURE.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None </dd></dl>

<p>References <a class="el" href="struct_x_dcfg___config.html#a97b0e40ed1632649e15eedea77e84a82">XDcfg_Config::BaseAddr</a>, <a class="el" href="struct_x_dcfg.html#aa781f458f64d74c8147d10f09683301e">XDcfg::Config</a>, <a class="el" href="xdevcfg__interrupt__example_8c.html#a286f17de7ab3285f143c9aab3fc26da4">SLCR_LOCK</a>, <a class="el" href="xdevcfg__interrupt__example_8c.html#af11ce8b1924394e9c6d481b9f4fd45dd">SLCR_LVL_SHFTR_EN</a>, <a class="el" href="xdevcfg__interrupt__example_8c.html#a4bb19a9df26550ba4c6fcaaddf516f18">SLCR_PCAP_CLK_CTRL</a>, <a class="el" href="xdevcfg__interrupt__example_8c.html#a83fcf6f141c914ab6b8b683fb62232b4">SLCR_UNLOCK</a>, <a class="el" href="group__devcfg.html#gafcaaa8ac67cf7316c54d1cba36e83e08">XDcfg_CfgInitialize()</a>, <a class="el" href="group__devcfg.html#gaac84a7176f99dc0e1d66a53673053228">XDCFG_CTRL_PCAP_PR_MASK</a>, <a class="el" href="group__devcfg.html#ga40ccdd2b121359e65b1f95e5f32be3d8">XDCFG_DMA_INVALID_ADDRESS</a>, <a class="el" href="group__devcfg.html#gabb2094cb7d36f83c4c150a3b18e8aad0">XDcfg_EnablePCAP()</a>, <a class="el" href="group__devcfg.html#ga3cb50f996ae2577642b7d1b91c33105f">XDcfg_InterruptHandler()</a>, <a class="el" href="group__devcfg.html#gafff047d176ced3a255248219c1278e3b">XDcfg_IntrClear()</a>, <a class="el" href="group__devcfg.html#gab7606b370c10d68d61402bed68955a80">XDcfg_IntrDisable()</a>, <a class="el" href="group__devcfg.html#gab9c70f073e4522d6085c0059bc385aa9">XDcfg_IntrEnable()</a>, <a class="el" href="group__devcfg.html#ga9ed5382e8c80a2277816a4db98a1ec6f">XDcfg_IntrGetStatus()</a>, <a class="el" href="group__devcfg.html#gae46a37df60109876c5f96d62dc6b9f78">XDCFG_IXR_D_P_DONE_MASK</a>, <a class="el" href="group__devcfg.html#ga219beab8ecbdaa4e74c8d130b94e4ae0">XDCFG_IXR_DMA_DONE_MASK</a>, <a class="el" href="group__devcfg.html#ga39c7e70832ef5a30a251342bf831f088">XDCFG_IXR_PCFG_DONE_MASK</a>, <a class="el" href="group__devcfg.html#gab7512afadad93e25630048943fd72d41">XDcfg_LookupConfig()</a>, <a class="el" href="group__devcfg.html#ga77561dc2e9ea13137f50a8193b8fbcd3">XDcfg_ReadReg</a>, <a class="el" href="group__devcfg.html#ga2c24756b9d6f8e81b620d27a86379e15">XDcfg_SelfTest()</a>, <a class="el" href="group__devcfg.html#gacc8c10b5cc877595c1ade09e1a589296">XDcfg_SetControlRegister()</a>, <a class="el" href="group__devcfg.html#gaed08df4afb0dd9c343bf994b4c18e926">XDcfg_SetHandler()</a>, <a class="el" href="group__devcfg.html#ga48a0c155d061c98656101cb19a87f0a0">XDCFG_STATUS_DMA_CMD_Q_F_MASK</a>, <a class="el" href="group__devcfg.html#ga6646b7874a5c9cc7bcdba6072bb4ff72">XDCFG_STATUS_OFFSET</a>, and <a class="el" href="group__devcfg.html#ga5a7a69cfe6e10770f82089bdd277955d">XDcfg_Transfer()</a>.</p>

<p>Referenced by <a class="el" href="xdevcfg__interrupt__example_8c.html#a840291bc02cba5474a4cb46a9b9566fe">main()</a>.</p>

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